Fig. 5

Decoding of columnar layout. An example is shown for decoding column 2 for quarter block Q2 from a block packed with a bit width of 6. Source code is listed in part (f), with key steps shown graphically in parts (a) through (e), and a final summation step in part (g). a, b Loading of two 128-bit vectors from the block. c Parallel (SIMD) right shift of each 32-bit word by 24 bits, to move \(d_2\), \(d_6\), \(d_{10}\), and \(d_{14}\) into the lowest 6 bits. d Recombining of \(d_{18}\), \(d_{22}\), \(d_{26}\), and \(d_{30}\), which are split between two 128-bit vectors in the block, using a parallel right shift of the first vector by 30 bits and a parallel left shift of the second vector by 2 bits. e Parallel addition of the first and second vector of differences. f Source code in the C language. Comments in the source correspond to the steps labeled a through e. g Difference results shown as an array of 32-bit words. The value \(x_7\) can be obtained by adding two terms from the array, while the value \(x_{23}\) can be obtained by adding four terms